Timing in a circuit, especially delay circuits, often requires adjustment based on studies on hardware. For example, in a dynamic random access memory (DRAM), the word line (WL) turn-on to the sense amplifier (SA) set timing signal controls the signal level at which the SA starts sensing. The design of timing circuits is based on simulation of detailed circuit models. However, the actual delay time required is often unclear. In some cases, test modes are implemented to add a pre-set delay or remove a pre-set delay for adjustment. Once the circuit is designed, the range of adjustment is limited and inflexible. It is therefore advantageous to provide for arbitrarily adjusting such internal timings externally with a tester.